1. Field of the Invention
The present invention relates to an exposure device and an exposure method. The invention also relates to a semiconductor device having a circuit that is composed of a thin film transistor (hereinafter referred to as TFT) made by using the exposure method, and to a method of manufacturing the same. The semiconductor device of the present invention includes not only elements such as thin film transistors (TFTs) and MOS transistors but also electrooptical devices, such as display devices and image sensors, having semiconductor circuits composed of those insulating gate type transistors. The semiconductor device of the invention relates to, for example, electrooptical devices typical example of which is a liquid crystal display panel or an electroluminescence (EL) display device and to electronic equipments provided with as their parts such electrooptical devices.
Incidentally, the semiconductor device in this specification refers to devices in general which can function by utilizing semiconductor characteristics. The electrooptical devices, the semiconductor circuits and the electronic equipments are therefore all fall into the semiconductor device.
2. Description of the Related Art
What has been receiving attention is an active matrix liquid crystal display device in which a pixel circuit and a driver circuit are composed of thin film transistors (TFT) formed over an insulating substrate. Liquid crystal displays in use as a display device vary in size, ranging approximately from 0.5 inch to 20 inch.
With the intention of realizing a liquid crystal display device capable of high definition display, attention is presently drawn to a TFT of which an active layer is made of a crystalline semiconductor film represented by a polysilicon film.
However, the TFT having an active layer of crystalline semiconductor film involves a problem in that the TFT is, on one hand high in operation speed and driving performance, but on the other hand large in leak current as compared to a TFT having an active layer of an amorphous semiconductor film.
Known as a technique to suppress this leak current is to form an LDD region between a channel forming region and drain region of the TFT. This LDD region serves to ease the intensity of the electric field formed between the channel forming region and the drain region, reduce OFF current of the TFT and prevent degradation.
In order to form the LDD region between the channel forming region and drain region of the TFT, a mask is used to dope a region to be the drain region with a high concentration of impurity ion for imparting conductivity and to dope a region to be the LDD region with a low concentration of impurity ion for imparting conductivity. As conventional methods for forming a mask used to thus selectively form regions different in dopant concentration, Patterning <1> (non self alignment method) and Patterning <2> (self alignment method) are enumerated. Patterning <1> uses a photo mask and Patterning <2> uses a wiring as a mask to perform exposure from the back side.
The Patterning <1> using a conventional photo mask is briefly described below. When an LDD structure is to be formed, a mask by photolithography is usually employed. The description here is made using a fabricating process of a bottom gate type TFT by way of example.
First, a gate wiring is formed over an insulating substrate. A first photo mask is used at this stage. Then, a gate insulating film and a semiconductor film having an amorphous region are formed over the gate wiring. The semiconductor film having an amorphous region is subjected to crystallizing process through heating, laser beam-irradiation or the like to form a crystalline semiconductor film.
A mask pattern is subsequently formed with the use of the Patterning <1>. The Patterning <1> here means to perform the steps of forming an insulating film for the mask pattern, applying a photoresist film onto the insulating film for the mask pattern, forming a photoresist pattern through exposure and development with the use of a second photo mask, etching the insulating film for the mask pattern to form a mask pattern while using the photoresist pattern as a mask, and removing the photoresist pattern. Such a method involving the use of a photo mask is called non self alignment method. Thereafter, the mask pattern is used to selectively dope the crystalline semiconductor film with an impurity ion for imparting conductivity, thereby forming a source region, a drain region, an LDD region or the like.
The problem accompanying this method is that characteristics of TFTs vary because the positioning of the photo mask is uneven in a certain range. High accuracy is required particularly in patterning the mask pattern, which determines the width of a channel forming region.
The Patterning <2> in which a wiring serves as a mask to expose from the back side is described with reference to FIGS. 14A to 14C. As compared with the Patterning <1>, patterning by exposure from the back side can attain higher accuracy. However, in patterning by exposure from the back side in prior art, light goes around and reaches over, resulting in a slightly narrower pattern than the width of the wiring.
First, a gate wiring 11 is formed over an insulating substrate 10. A first photo mask is used at this stage. Then, a gate insulating film 12 and a semiconductor film having an amorphous region are formed over the gate wiring. The semiconductor film having an amorphous region is subjected to crystallizing process through heating, laser beam irradiation or the like to form a crystalline semiconductor film 13.
A mask pattern is subsequently formed with the use of the Patterning <2>. The Patterning <2> here means to perform the steps of forming an insulating thin film 14 for the mask pattern, applying a photoresist film 15 onto the insulating thin film for the mask pattern (FIG. 14A), forming a resist pattern 16 through exposure from the back side with the use of gate wiring as a mask and development (FIG. 14B), etching the insulating film for the mask pattern to form a mask pattern 17 while using the resist pattern as a mask, and removing the resist pattern 16 (FIG. 14C). Formed through this exposure from the back side is the mask pattern 17 which has almost the same size as the gate wiring. In FIGS. 14A to 14C, the end of the resist pattern and the wiring end coincide with each other. However in fact, light rounds to make the mask pattern 17 shorter than the gate wiring, spacing apart their ends by about 0.3 to 0.5 μm.
Such a method that does not use a photo mask is called self alignment method. Thereafter, the mask pattern is used to selectively dope the crystalline semiconductor film with an impurity ion for imparting conductivity, thereby forming a source region, a drain region or an LDD region.
The problem this method <2> gives rise to is that forming the resist pattern as desired is difficult because the resist pattern can be formed only one having almost the same size as the gate wiring used for a mask. Although it is possible to form the resist pattern within the gate wiring area by changing exposure conditions such as exposure time to make the light round, the light reaches over to cause reduction in film thickness of the resist pattern. For that reason, particularly when a minute wiring is used as a mask, the method is not suitable, for a fear that the entire resist over the wiring may be exposed. If the light rounds, it merely reaches somewhere 1 μm far from the end, at most. In addition, to cause the light to round and reach the point about 1 μm far from the end, considerable exposure time and exposure light quantity are required.
Consequently, it has been needed to conduct selective doping using masks by the Patterning <1> and the Patterning <2> when an LDD region is formed in a process of manufacturing a bottom gate type TFT.